EC6302 Digital Electronics | Important Questions | Question bank | Syllabus | Model and Previous Question papers | Download PDF

EC6302 Digital Electronics

EC6302 Digital Electronics | Important  Questions | Question bank | Syllabus | Model and Previous Question papers | Download PDF Exammain.com Important Questions is available for download in this page for EC6302 Digital Electronics . Students can download the Important Questions in the PDF format or in Word format. Questions Bank and Previous year question papers also be available in this page  . Important Questions provided here are the Expected questions that are possible to be appeared in the upcoming exams. you can make use of the below questions and prepare for your exams. EC6302 Digital Electronics Important Questions . Download the Important Questions using the below link.

Subject Information : 

University        :  Anna University
Department     :  B.E. ELECTRONICS AND COMMUNICATION ENGINEERING
Semester          : 03 th sem
Year                  : 02 nd year
Regulation       : R2013
Subject Code   : EC6302
Subject Name  : Digital Electronics

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EC6302 Digital Electronics  | Important  Questions
Syllabus	Click Here to Download
Part A Important Questions	Click Here to Download >>
Part B Important Questions	Click Here to Download  >>
Question Bank	Click Here to Download
Full Study Material	Click Here to Download
Other Subject Important Questions	Click Here to Download

EC6302 DIGITAL ELECTRONICS – SYLLABUS – R- 2013 

OBJECTIVES:

 To introduce basic postulates of Boolean algebra and shows the correlation between Boolean
expressions
 To introduce the methods for simplifying Boolean expressions
 To outline the formal procedures for the analysis and design of combinational circuits
 and sequential circuits
 To introduce the concept of memories and programmable logic devices.
 To illustrate the concept of synchronous and asynchronous sequential circuits

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

Minimization Techniques: Boolean postulates and laws – De-Morgan‟s Theorem – Principle of
Duality – Boolean expression – Minimization of Boolean expressions –– Minterm – Maxterm – Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don‟t care conditions – Quine – Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR Implementations of Logic Functions using gates, NAND–NOR implementations – Multi level gate implementations- Multi output gate implementations. TTL and CMOS Logic and their characteristics – Tristate gates

UNIT II COMBINATIONAL CIRCUITS

Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor – Parallel binary
adder, parallel binary Subtractor – Fast Adder – Carry Look Ahead adder – Serial Adder/Subtractor –
BCD adder – Binary Multiplier – Binary Divider – Multiplexer/ Demultiplexer – decoder – encoder –
parity checker – parity generators – code converters – Magnitude Comparator.

UNIT III SEQUENTIAL CIRCUITS

Latches, Flip-flops – SR, JK, D, T, and Master-Slave – Characteristic table and equation –Application
table – Edge triggering – Level Triggering – Realization of one flip flop using other flip flops – serial
adder/subtractor- Asynchronous Ripple or serial counter – Asynchronous Up/Down counter –
Synchronous counters – Synchronous Up/Down counters – Programmable counters – Design of
Synchronous counters: state diagram- State table –State minimization –State assignment – Excitation
table and maps-Circuit implementation – Modulo–n counter, Registers – shift registers – Universal shift registers – Shift register counters – Ring counter – Shift counters – Sequence generators.

UNIT IV MEMORY DEVICES

Classification of memories – ROM – ROM organization – PROM – EPROM – EEPROM –EAPROM,
RAM – RAM organization – Write operation – Read operation – Memory cycle – Timing wave forms – Memory decoding – memory expansion – Static RAM Cell- Bipolar RAM cell – MOSFET RAM cell – Dynamic RAM cell –Programmable Logic Devices – Programmable Logic Array (PLA) –
Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) – Implementation of
combinational logic circuits using ROM, PLA, PAL

UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Synchronous Sequential Circuits: General Model – Classification – Design – Use of Algorithmic
State Machine – Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits – Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG.

Also check :

EC6302 Digital Electronics Important Notes – Click here to Download 

EC6302 Digital Electronics Important Questions Papers – Click here to Download 

EC6302 Digital Electronics Important 2 marks with answers – Click here to Download 

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